1. Field of Invention
This invention relates to semiconductor memories and in particular flash electrically erasable and programmable read only memories (EEPROM) for use in mass storage applications.
2. Description of Related Art
A major driving force behind semiconductor flash memory devices has been the cost per bit reduction achieved by reduction of cell sizes by utilizing process scaling techniques. An attempt to accelerate the rate cost reduction has fostered several ongoing activities to develop reliable multiple bits per storage cell devices and reduction in cell size using innovative cell architecture.
In the Intel Technology Journal, 4th quarter 1997, "Intel StrataFlash.TM. Memory Technology Overview", (Atwood et al.), a stacked gate structure is described in which an ETOX process is used to produce a multiple level cell to store two bit in the same memory cell. In U.S. Pat. No. 5,828,600 (Kato et al.) is described a nonvolatile semiconductor memory where the cells are a MOSFET with a floating gate and have low power, high speed and reduced cell area. An additional objective of the invention is to insure the number of program and erase operations of 10.sup.6. In U.S. Pat. No. 5,400,279 (Momodomi et al.) discloses a nonvolatile memory device with a NAND cell structure. In U.S. Pat. No. 5,095,344 (Harari) a highly compact flash memory device is disclosed using an intelligent programming technique to allow multiple bits to be stored in each cell and an intelligent erase program to extend the useful life of each cell. In U.S. Pat. No. 5,029,130 (Yeh) a single transistor electrically programmable and erasable memory cell is disclosed using a spit gate which allows the control gate to control a portion of the channel and the floating gate to control the remaining portion of the channel.
There arc several approaches in prior art to form nonvolatile memories potentially suitable for mass storage requirements. These approaches range from storing more than one bit of information in a cell to producing highly compact devices to using different architecture that create NAND and AND arrays to minimize the die size. As history has shown there is a relationship between larger memory density, higher utilization and lower memory price, and this seems to track for flash memories as well. Much of the improvement to date has been through smaller geometry's. Flash memory's are used in a wide array of products, and the non volatility makes a flash memory a candidate for mass storage applications.